•The 8086 operates in
–minimum mode (single processor mode )
–maximum mode (multiprocessor mode ) high performance.
•The 8086 signals are classified in three groups
–common functions in minimum & maximum mode.
–special functions in minimum mode
–special functions in maximum mode.
Common signals for both modes
• AD0-AD15 :
These are the time multiplexed address and data bus. It carries address during T1 state or data during remaining T state of machine cycle. (T2, T3, Tw and T4.) Tristate during interrupt acknowledge and local bus hold acknowledge cycles.
•A19/S6,A18/S5,A17/S4,A16/S3 :
These are the time multiplexed address and status lines. During T1 state carries most significant address or status during remaining T state of machine cycle. (T2, T3, Tw and T4).
BHE#/S7 :
•The bus high enable is used to indicate the transfer of data over the higher order ( D8-D15).
• It is low when data is being transfer over D8-D15 bus.
•It is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus.
•The status information is available during T2, T3 and T4.
•The signal is active low and tristated during hold.
RD# – Read
•When it is low, 8086 reads data from the peripheral. i.e. 8086 is performing s memory or I/O read operation.
•RD is active low and shows the state for T2, T3, Tw of any read cycle.
•The signal remains tristated during the hold acknowledge.
READY :
•It is active high signal.
•This is the acknowledgement from the slow device or memory that they have completed the data transfer.
•The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086.
RESET :
•The signal is active high and must be active for at least four clock cycles.
•This input causes the processor to terminate the current activity and start execution from FFF0H.
•It restarts execution when the RESET returns low.
•IT is also internally synchronized.
INTR-Interrupt Request :
•This is a level triggered input.
•This signal is active high
•This is checked during the last clock cycles of each instruction.
•If any interrupt request is pending, the processor enters the interrupt acknowledge cycle.(ISR)
•This can be internally masked by resetting the interrupt enable (EN) flag.
NMI- Nonmaskable interrupt :
•This is an edge triggered input which causes a Type 2 interrupt.
• The NMI is not maskable internally by software.
•Rising edge initiates the interrupt response at the end of the current instruction.
•This input is internally synchronized.
TEST# :
•This signal is used to check the status of math co-processor 8087.
•This input is examined by a ‘WAIT’ instruction.
•If the TEST# pin goes low, execution will continue, else the processor remains in an idle state.
CLK- Clock Input :
•The clock input provides the basic timing for processor operation and bus control activity.
• Its an asymmetric square wave with 33% duty cycle.
Vcc +5V power supply for the operation of the internal circuit.
GND ground for internal circuit.
MN/MX# :
•The logic level at this pin decides whether the processor is to operate in either minimum or maximum mode.
•When it is high 8086 operates in minimum mode.
•When it is low 8086 operates in maximum mode.
Minimum mode signals
WR# – Write
•When it is low, 8086 writes data to the peripheral. i.e. 8086 is performing s memory or I/O write operation.
•WR is active low and shows the state for T2, T3, Tw of any read cycle.
•The signal remains tristated during the hold acknowledge.
ALE – Address Latch Enable
•It is output signal.
• When it is 1, AD0-AD15 carries address. When it is 0, AD0-AD15 carries data.
•During T1 state of every machine cycle it is high. During T2, T3 and T4, it is low.
DEN# – Data Enable
•This signal indicates the availability of valid data over the address/data lines.
•It is used to enable transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal.
•It is active from the middle of T2 until the middle of T4. This is tristated during hold acknowledge cycle.
DT/R# – Data Transmit/Receive
•It is output signal.
•It is used to decide the direction of data flow. (through the transreceivers i.e. bidirectional buffers).
• When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low.
M/IO# – Memory/IO#
•It is output signal.
•When it is low, it indicates the CPU is having an I/O operation.
•When it is high, it indicates that the CPU is having a memory operation.
INTA# – Interrupt Acknowledge ( Active Low)
•When 8086 accepted the interrupt, INTA# goes low & 8086 enters into interrupt acknowledge cycle.
HOLD, HLDA- Acknowledge :
•When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access.
• The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, (in the middle of the next clock cycle) after completing the current bus cycle.
Maximum mode signals
•S0#, S1# & S2# – Status Lines :
•These are the status lines which reflect the type of operation, being carried out by the processor.
•These are applied to bus controller 8288 to generate MEM & IO control signals.
•These become active during T4 of the previous cycle and remain active during T1 and T2 of the current bus cycles.
